Data serializers are well-known in a common use in various electronic devices. The function of a data serializer is to convert parallel data into a corresponding stream of serial data. Data serializers are sometimes used in integrated circuit devices where data may be coupled to or from an electronic device at a significantly faster rate than the data can be processed within the device. For example, in integrated memory devices, data may be coupled to or from a memory device at a rate that may be significantly faster than the rate at which the data may be serially processed in the memory device. In such case, for example, read data may be provided by an array of memory cells in the memory device as a large number of parallel digits (e.g., bits), which are converted to a corresponding stream of serial data and output through a serial data port.
Although the design parameters of serializers may vary for different applications, two design parameters that may be considered for memory devices are power consumption and operating speed. Operating speed may be important to allow read data to be transmitted from a memory device with a high data bandwidth. Low power consumption may be important in various applications, such as where a memory device is used in a battery-powered electronic system, such as a laptop computer.
Prior art serializers typically may use a sampling circuit, such as a latch, for each parallel data that is to be serialized. Thus, for example, 16 sampling circuits may be used to convert 16 digits of parallel data to a corresponding serial stream. The sampling circuit may obtain a sample of the data digit and output the sample at an output node responsive to a transition of a received clock signal. Each sampling circuit may receive a clock signal having a different phase. The output nodes of all of the sampling circuits used in the serializer may be connected to each other so that the sampling circuits sequentially apply the respective samples to the output nodes.
Prior art sampling circuits may typically use an output stage having several transistors connected to the output node of the sampling circuit. As a result, the capacitance of the output node may be fairly large. The capacitance is further increased because Prior art sampling circuits may typically switch the output node between two voltages. Further, since the output nodes of a large number of sampling circuits may be coupled to each other, the capacitance at the output nodes of the sampling circuits are connected to each other in parallel, thus resulting in a substantial capacitance at the combined output nodes.
The large capacitance that may be present at the output node of a serializer may limit the operating speed of the serializer, thereby potentially limiting the data bandwidth of the memory device. Additionally, a large capacitance may require that serializers provide larger currents to drive the output node, thereby potentially resulting in increased power consumption. In fact, higher operating speeds may sometimes only be achieved at the expense of increased power consumption.